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Quad Flat Packages · infineon-psoc-5lp-cy8c56lp-datasheet-datasheet-en.pdf · GPT-5.4 ·
The model flagged this extraction for review.
0 of 1 decided
100-pin TQFP
Also considered: 68-pin QFN
0 of 13 decided
Body Length
14.00 ± 0.05 mm
Body Width
14.00 ± 0.05 mm
Height
1.40 ± 0.05 mm
Left/Right Pins
25
Pin Length
0.60 ± 0.15 mm
Pin Pitch
0.50 mm typ
Pin Span 1
16.00 ± 0.20 mm
Pin Span 2
16.00 ± 0.20 mm
Pin Width
0.22 ± 0.05 mm
Stand Off
0.05 min / 0.15 max mm
Thermal Pad Length
Not in datasheet
Thermal Pad Width
Not in datasheet
Top/Bottom Pins
25
0 of 100 decided
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWDIO, TMS
P1[1], SWDCK, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], NTRST
VDDIO1
P1[6]
P1[7]
P12[6], SIO
P12[7], SIO
P5[4]
P5[5]
P5[6]
P5[7]
USB D+, P15[6]
USB D-, P15[7]
VDDD
VSSD
VCCD
NC
NC
P15[0], MHZXOUT
P15[1], MHZXIN
P3[0], IDAC1
P3[1], IDAC3
P3[2], OA3-, REF1
P3[3], OA3+
P3[4], OA1-
P3[5], OA1+
VDDIO3
OA1OUT, P3[6]
OA3OUT, P3[7]
SIO, P12[0]
SIO, P12[1]
KHZXOUT, P15[2]
KHZXIN, P15[3]
NC
NC
NC
NC
NC
NC
VCCA
VSSA
VDDA
VSSD
SIO, P12[2]
SIO, P12[3]
P4[0]
P4[1]
OA2OUT, P0[0]
OA0OUT, P0[1]
OA0+, SAR1REF, P0[2]
OA0-, REF0, P0[3]
VDDIO0
OA2+, SAR0REF, P0[4]
OA2-, P0[5]
IDAC0, P0[6]
IDAC2, P0[7]
P4[2]
P4[3]
P4[4]
P4[5]
P4[6]
P4[7]
VCCD
VSSD
VDDD
P6[0]
P6[1]
P6[2]
P6[3]
P15[4]
P15[5]
P2[0]
P2[1]
P2[2]
P2[3]
P2[4]
VDDIO2
Baseline and 1 run
| Run | Agreement | Latency | Est. cost | Date | Open |
|---|---|---|---|---|---|
GPT-5.4Baseline Not started | —Not applicable | — | — | Viewing | |
Terra · Medium Not reviewed | vs unreviewed baseline | 48.3 s | $0.87 | Open run Terra · Medium |
J / K move · C confirm · X incorrect · N next pending · ? all shortcuts
0 / 114 decided